FIG. 15 is a diagram illustrating the basic constitution of a hysteresis-type input circuit used in digital circuits in the prior art. FIG. 17 is a diagram illustrating the waveforms of various portions of said input circuit.
Hysteresis circuit 100 contained in said hysteresis-type input circuit, for example, has the hysteresis-type input/output transmission characteristic shown in FIG. 16. More specifically, for voltage Vin of input signal Sin, a lower trip point LTP (lower trip point) having a prescribed value and an upper trip point UTP (upper trip point) having a prescribed value exist. When input voltage Vin rises from the L level stable value or minimum value LVin (usually 0 V) to the H level stable value or maximum value HVin, UTP becomes the threshold. When original input voltage Vin is lower than UTP and output voltage Va is at the H level, as input voltage Vin rises above UTP, output voltage Va is instantly inverted from the H level to the L level. When input voltage Vin falls from H level stable value HVin to L level stable value LVin, LTP becomes the threshold. When original input voltage Vin is higher than LTP and output voltage Va is at the L level, as input voltage Vin falls below LTP, output voltage Va is instantly inverted from the L level to the H level.
In this way, in hysteresis circuit 100, with respect to a rise of input voltage Vin from the L level to the H level, a first output inversion operation is performed with inversion of output voltage Va from the H level to the L level at UTP. With respect to a fall of input voltage Vin from the H level to the L level, a second output inversion operation is performed with inversion of output voltage Va from the L level to the H level at LTP. The state in the circuit when said first output inversion operation is performed (the first state) and the state in the circuit when the second output inversion operation is performed (the second state) are different from each other. After performing the first output inversion operation, transition occurs to the second state. After performing the second output inversion operation, transition occurs to the first state. Said transitions are not performed instantly, and there is a time-delay before completion.
As shown in FIG. 15, in the conventional hysteresis-type input circuit, on the output side of hysteresis circuit 100, one or several stages of inverter 102 (three stages in the example shown in the figure: (102A), (102B), (102C)) for waveform shaping or line driving are set in a cascade connection. In this case, in hysteresis circuit 100, when output voltage Va is changed from the L level to the H level or from the H level to the L level with input voltage Vin at LTP or UTP, it passes by the inversion threshold of the downstream inverter, especially the inversion threshold Vta of the first stage inverter (102A). Corresponding to this, the logic level of output voltage Vb of inverter (102A) is inverted. In the downstream inverters (102B), (102C), too, the same output inversion operation is performed as a chain, and, in the output of the last stage inverter (102C), binary signal Sout having voltage Vd of the same logic level as that of voltage Vin of input signal Sin in the steady or DC (direct current) state.
As shown in FIG. 17, in said hysteresis-type input circuit, even when glitches G1, G2 are riding on a rising waveform or a falling waveform of input signal Sin between LTP and UTP, said glitches G1, G2 are masked with the hysteresis input/output characteristic of hysteresis circuit 100 with said constitution, so that noise pulses are not displayed on output signal, Sout.
However, for said conventional hysteresis-type input circuit with the aforementioned constitution, when a glitch (such as glitch G3 shown in FIG. 17) that arrives near LTP or UTP rides on a rising waveform or a falling waveform of input signal Sin, the noise pulse corresponding to said glitch G3 may be transmitted on the downstream signal transmission path. In the following, the case when a noise pulse is generated due to said glitch will be explained with reference to FIG. 18.
As shown in FIG. 18, at time t1 when input voltage Vin crosses LTP during the course of its fall, hysteresis circuit 100 performs a second output inversion operation. Corresponding to this operation, in downstream inverters (102A), (102B), (102C), the output inversion operations are performed as a chain, and voltage Vd of output signal Sout is changed from the hitherto H level to the L level. When hysteresis circuit 100 performs the second output inversion operation at said time t1, transition starts from the hitherto state, that is, the second state, to the first state as the state in which the first output inversion operation can be performed at UTP.
However, in the case of glitch G3 shown in the figure, once input voltage Vin crosses LTP and then rises immediately, output voltage Va that was higher than inversion threshold Vta turns to fall. When there is a large rise and change of glitch G3, although input voltage Vin is lower than UTP, output voltage Va crosses inversion threshold Vta. That is, the same result as obtained in the first output inversion operation at UTP appears in the output of hysteresis circuit 100. From another viewpoint, as shown in FIG. 18, when the rising change of input voltage Vin rises above floating trip point UTP′ during its course as it changes (rises) to UTP, the same abnormal output inversion operation as the first output inversion operation is performed, and output voltage Va crosses inversion threshold Vta. Corresponding to this operation, in the downstream inverters (102A), (102B), (102C), the output inversion operation is performed as a chain, and voltage Vd of output signal Sout returns from the L level to the H level at an undesired timing.
Then, in hysteresis circuit 100, at time t2 when the output inversion operation is performed abnormally at UTP′, the distribution of transition is inverted to the second state. However, in the case of glitch G3 as shown in the figure, input voltage Vin rises above floating trip point UTP′ and then immediately turns back and falls. As this falling change crosses floating trip point LTP′ during the course of its transition (fall) towards LTP, at this time t3, the same abnormal output inversion operation as that of the second output inversion operation is performed, and output voltage Va again rises above inversion threshold Vta. As a result, corresponding to this operation, downstream inverters (102A), (102B), (102C) perform output inversion operations as a chain, and voltage Vd of output signal Sout returns from the H level to the L level. In this way, an undesired pulse or glitch pulse np corresponding to glitch G3 is transmitted to the downstream circuit, not shown in the figure.
When the operation of inverters (102A), (102B), (102C) is delayed, it becomes impossible to follow the minuscule-yet-fast change as a glitch. Consequently, it is also possible to mask a glitch pulse with said inverters. However, with progress in semiconductor process technology in recent years, transistors have achieved higher-speed operation, and it is quite possible that a glitch pulse will pass and be transmitted to a downstream or internal circuit.
A general object of the present invention is to solve the problems of the prior art by providing a hysteresis-type input circuit characterized by the fact that for any glitch riding on the voltage waveform of the input signal, it can always guarantee stable hysteresis characteristic, and an undesired pulse waveform will not be transmitted to the downstream circuit.